1. Field of the Invention
This invention relates to semiconductor packages, and, more particularly, to a method of testing a semiconductor package.
2. Description of Related Art
Due to the capabilities of reducing a chip packaging area and shortening a signal transmission path, a flip-chip technique can be applied to a variety of chip packaging fields, such as a chip scale package (CSP), a direct chip attached (DCA) package, and a multi-chip module (MCM) package.
In a flip-chip package fabrication process, since the coefficients of thermal expansion (CTE) of a semiconductor chip and a substrate that is greater than the semiconductor chip in area differ significantly, conductive bumps surrounding the semiconductor chip are in poor electrical contact with electrical contacts disposed on the substrate (since the semiconductor chip has a small size, the conductive bumps are also small in volume, and the attachment between the conductive bumps and the substrate is weak), and are thus likely to be stripped from the substrate.
With the increase of the integrity of integrate circuits disposed on the semiconductor chip, the thermal stress and warpage phenomenon generated due to the mismatch of CTEs of the smaller semiconductor chip and the larger substrate are more and more severe. As a result, the reliability between the semiconductor chip and the substrate is reduced, and a reliability test fails accordingly.
In the prior art, a plurality of chips are disposed on the substrate in a two-dimension manner. The larger the number of the chips is, the greater the area of the substrate becomes, which does not comply with the compact-sized and low-profiled requirements for modern electronic products.
In order to solve the problem, a semiconductor package is brought to the market. As shown in FIG. 1, a plurality of through silicon vias (TSV) 111 are formed in a whole silicon wafer, a redistribution layer 12 is formed on a side of the silicon wafer where a semiconductor chip 14 is to be disposed, solder balls 13 are disposed on the other side of the silicon wafer where a substrate 16 is to be disposed, a singulation process is performed to form a plurality of silicon interposers 11, the semiconductor chip is disposed on the silicon interposers 11 via bumps 18, an underfill 15 is formed between the semiconductor chip 14 and the silicon interposer 11, the silicon interposers 11 are disposed on the substrate 16, an underfill 17 is formed between the silicon interposer 11 and the substrate 16, and a plurality of solder balls 19 are disposed on a bottom surface of the substrate 16 where the silicon interposers 11 are not disposed. Since the silicon interposer 11 and the semiconductor chip 14 are made of similar materials, and the problem due to the mismatch of CTEs is solved. Since both a circuit on a side of the silicon interposer 11 where the semiconductor chip 14 is disposed and contacts or a circuit on the semiconductor chip 14 that are to be connected with the circuit are fabricated by a semiconductor wafer fabrication process, a plurality of the semiconductor chips 14 can be disposed on the silicon interposer 11, with an area not increased. In order to comply with functional design or circuit design requirements, the semiconductor chips are stacked on one another, to comply with the compact-sized and low-profiled requirements for modern electronic products. The underfills 15 and 17 protect the solder balls 13 and the bumps 18 from being contaminated by ambient environment.
Compared with the old technique that disposes a semiconductor chip that has a smaller area on a substrate directly, the semiconductor package uses the silicon interposer 11 as an intermediate board. The silicon interposer 11 is fabricated by a semiconductor process, and can have a line width/line pitch as small as the semiconductor chip 14. Therefore, the semiconductor chip 14 can be disposed on the silicon interposer 11 and connected to the substrate 16, and the overall volume of the semiconductor package is reduced. The small line width/line pitch characteristics of the silicon interposer 11 also correspond to a shortened electrical connection distance. Therefore, the overall electrical transmission speed is increased.
However, in a method of testing a semiconductor package according to the prior art a semiconductor chip 14 is first disposed on the silicon interposer 11 on the substrate 16 and a first electrical test step is then performed via the solder balls 19; and, after the first electrical test step is successful, another semiconductor chip 14 is disposed on the silicon interposer 11 and a second electrical test step is performed, in order to avoid a drawback that both the two semiconductor chips 14 have to be declared to be mal-functional even if only one of the two semiconductor chips 14 cannot pass the electrical test step, because both the two semiconductor chips 15 have been disposed on the silicon interposer 11. Besides, the electrical test steps of the prior art take much time, and, as such, the overall throughput drops.
Therefore, how to solve the problems of the prior art is becoming an urgent issue in the art.